Intel introduced the FinFET process technology with the norms of 10 nm and 22 nm

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POSTER: computer news   ||    INTEL INTRODUCED THE FINFET PROCESS TECHNOLOGY WITH THE NORMS OF 10 NM AND 22 NM	DATE:2017-03-29
Intel again confirmed that in the second half of the year it will release the most advanced 10nm solutions in the industry in the face of Cannonlake processors.  The company does not bother at all that TSMC and Samsung have started mass production of 10-nm chips. According to Intel representatives  , none of the competitors is capable of producing such a perfect 10-nm solution as it is.  To prove this, Intel proposed a new technique for calculating transistors on a chip.  The old technique, which relied on measuring the physical distances between closures and metalization contacts, had long since outlived itself.  The shutter step does not correspond to the numbers describing the new process technology for a long time.  For example, for Intel's 10-nm process with FinFET transistors, the gate spacing is 54 nm. According to Intel, a new technique for determining the process technology for completeness of the picture should be based on the density of placement of transistors on the chip.  So, 10-nm FinFET technical process of the company allows to place 100.8 million transistors on one square millimeter.  For comparison, 10-nm FinFET technology companies Samsung and TSMC on a square millimeter give the opportunity to place a total of 50 million transistors.   It should be said that the company is not interested in all the transistors on the chip, but only those that are responsible for elementary logic.  So, a simple two-input NAND cell with at least two gates (shutters) and a simple trigger with a minimum of 25 gates should take part in the calculation.  In this case, NAND elements are counted with a weighting factor of 0.6, and triggers with a weighting factor of 0.4.  It will be interesting to hear the comments of TSMC and Samsung.  However, given the proliferation of tools for automatic design,   Intel proposal can make sense for creating a universal methodology. Also, Intel gave a detailed description of the branded 10-nm process technology being introduced into production and clearly showed its advantage over the 14-nm process technology.  So, the solutions will be produced using a four-step projection with self-aligning templates and promise the following geometry: FinFET edge step is 34 nm, FinFET edge height is 53 nm (rib height was increased by 25% to keep the gate area), metallization step is 36 nm , The gate step is 54 nm, the cell height is 272 nm.  The process technology with 10 nm standards will survive three generations (10, 10+ and 10 ++), as well as the current 14-nm process technology.  By the way, the technological process of 14 ++, with the help of which new desktop processors Intel Coffee Lake will be manufactured at the end of the year, will provide more productive solutions than the first 10-nm process technology. In addition to the 10 nm process, Intel developed two improvements in the topology of the transistors, which allowed for a 10% increase in density (contact-over-active-gate, COAG) and further single dummy gate. Interestingly, Intel does not hope for a single reduction in the scale of technological norms.  To compete with the expected 22-nm process technology using the plates from completely depleted silicon (FD-SOI), the company presented a "simplified" 22-nm process with FinFET transistors (22FFL).  Note, the technical process of GlobalFoundries and Samsung for 22nm standards and FD-SOI plates implies the use of planar transistors, so Intel's proposal in the face of 22FFL promises not the worst solution for mass chips.  For example, the 22FFL process technology for energy-efficient solutions, and there will also be a 22FFL process technology for production solutions, promises a 100-fold reduction in leakage currents. The Intel 22FFL technology promises a 45-nm pitch between the ribs, a 108-nm step between the gates, a 90-nanometer pitch between the metallization (using only one photo mask), 630-nm logic cell height, 18.8 million transistors / mm2 and SRAM cell area 0.88 �m2.  For the current 22-nm process FinFET, the gate and metallization step was smaller, 90 and 80 nm, respectively.  The 22FFL process technology will provide a commercially available industry with connectivity to the Internet and the network industry. Finally, the company gave the characteristics of the technical process with the norms of 14 nm of the latest generation (14 ++).  With its use, the third generation of x86-compatible processors, Altera Stratix 10 matrixes, LTE modems and more will be released.  For these solutions, the edge pitch will be 42 nm, the metallization step is 52 nm, the gate step is 70 nm, the cell height is -399 nm, the number of transistors per mm2 is 37.5 million, the SRAM cell area is 0.05 �m2.  The projection uses a spontaneous lithography. Related Products :

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