Specifications PCIe 4.0 will see the light this year, and PCIe 5.0 in 2019

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POSTER: computer news   ||    SPECIFICATIONS PCIE 4.0 WILL SEE THE LIGHT THIS YEAR, AND PCIE 5.0 IN 2019	DATE:2017-08-30
We already reported that in July and August the final discussions of the draft specifications of the standard (interface) PCI Express versions 4.0 and 5.0 are conducted.  The PCIe 4.0 version received the ordinal number 0.9, which is close to the final approval of the standard, and the PCIe 5.0 version is ready in stage 0.3, which means a fairly early stage of the process.  Nevertheless, the process is on its way, and at the recent annual Hot Chips 2017 event, representatives of the responsible organization PCI-SIG confirmed the terms of acceptance of the final versions of PCI Express 4.0 and 5.0. It should be noted that adoption of PCI Express 4.0 specifications has been extremely protracted.  The version of PCI Express 3.0 was introduced in 2010.  The PCI Express 4.0 version will be developed and available to a wide range of developers in late 2017.  Instead of the usual 4-year cycle of updating the standard, the new version had to wait for 7 years. In the last couple of years the industry has faced a lack of bandwidth of the PCI Express 3.0 bus.  Intensive calculations for the needs of artificial intelligence have chosen the potential of this high-speed interface.  A similar story occurs in the field of corporate data storage, which began with the expansion of SSD with support for the NVMe protocol.  Both these factors, as well as a number of other reasons, lead to the fact that the PCI Express 4.0 standard will be a temporary.  It will be replaced quickly - in 2019 (in two years!) Should come standard PCI Express 5.0 with twice the bandwidth. For PCI Express 4.0 specifications, as is known, the data transfer rate on one line will be increased from the current 8 Gbit / s to 16 Gbps (conditionally, some of the data in the package goes to the interface maintenance and does not bear useful information).  The PCI Express 5.0 specification provides for a transfer rate of 32 Gbps per line.  As in the case of PCI Express 3.0, the encoding will be 128b / 130b with redundant coding of 1.5%.  Simplified (or aggressive) coding already during the transition from version 3.0 to version 4.0 gives an overall reduction in redundancy of 20%, which will have a positive impact on energy efficiency and on useful throughput.   In the fourth quarter, as already mentioned, the adoption of PCI Express 4.0 specifications (final version) and draft specifications PCI Express 5.0 version 0.5 is expected.  A number of vendors have already developed or are completing the development of controllers supporting PCI Express 4.0.  Such a controller, for example, can be found in IBM Power9 processors.  Intel and AMD, according to rumors, before 2020, the PCI Express 4.0 bus in their platforms is unlikely to use.  Or they will surprise us? Related Products :

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